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| 1/26 STLC1512 november 2000 this is preliminary information on a new product now in development. details are subject to change without notice. n low power architecture -- class ab, current drive, output stage through a centre tapped transformer to facilitate power supply switching between 5.0v and a lower voltage. (3.3v in the reference design) this gives a reduction in power consumption. n 480mw power consumption with a typical g.lite signal. n 600ma current driving capability n positive +5.0v and one lower supply. (3.3v in the reference design) n switching power supplies to save power n thermal overload shutdown n four programmable receive gains n opamp for a low pass filter in the receive path n undedicated opamp with separate power down control (used as a transmit path filter in the reference design) n separate power down control for tx and rx path n 48-pin tqfp (7x7x1.4mm) package 1.0 general description the STLC1512 g.lite line driver chip contains the line driver as well as part of the receive path required in a central office g.lite modem. it provides an interface between the afe chip (stlc1511) and the tele- phone line. the line driver chip has been designed with low power consumption, high signal to noise plus distortion ratio and high current driving capabili- ty. tqfp48 (7x7x1.40) ordering number: STLC1512 product preview northenlite? g.lite loop driver figure 1. block diagram txang rbias rxpd lpfout lpfin ref2p5 dcfbon dcfbop fpn fpp pa i p pa i n pwrveex pao p x buffp buffn pa o n x pga rx ref buffer lpf amp bias thermal shutdown preamp power stage dc feedback amp opamp tx ref buffer amppd txpd pgain pga1 pga0 rxang dcfbin dcfbip ampip ampin ampout pgaout
STLC1512 2/26 1.0 general description the line driver transmit path contains a preamplifier followed by a power output stage. the power stage has current outputs that directly drive the primary side of a center tapped transformer. the receive path contains a programmable gain am- plifier followed by an opamp which is used with off chip passive components in an active low pass filter. the programmable grain amplifier (pga) has four steps optimized for the recommended g.lite co line interface. there is also an undedicated opamp which can be used for active filtering in either the transmit or re- ceive paths 2.0 packaging and pin information 2.1 package technology STLC1512 will be packaged in a tqfp 48 package, according to jedec specification reference ms- 026-bbc. 2.2 STLC1512 pin allocation the pin out for the STLC1512 is depicted in the fol- lowing figure 2. figure 2. STLC1512 pinout nc 48 1 tqfp48 (7x7x1.4mm) txang rbias pgaout pgain rxang rxvcc1 rxvcc2 rxvee1 txpd qveerx pga1 pga0 rxvee2 amppd rxpd lpfout lpfin nc ref2p5 dcfbon dcfbop fpn fpp pa i p pa i n ampip ampin ampout txvcc3 txvcc2 txvcc1 txvee1 txvee2 txvee3 qveetx dcfbip dcfbin pwrvee1 pwrvee2 pa o p 1 pa o p 2 buffp buffn pa o n 1 pa o n 2 pwrvee3 pwrvee4 3/26 STLC1512 2.3 pin description the pin description for the STLC1512 is given in the following table 1. table 1. pin description pin # pin name pin type pin description 1 1 pgaout ao rx pga output (programmable gain amplifier) 2 pgain ai rx pga input 3 rxang ao 2.5v rx buffered reference 4 rxvcc1 vcc +5.0v supply for rx path circuitry 5 rxvcc2 vcc +5.0v supply for rx path circuitry 6 qveerx vee quiet ground for the rx circuitry 7 rxvee1 vee ground for rx path circuitry 8 rxvee2 vee ground for rx path circuitry 9 pga0 di pga gain setting control bit 0 10 pga1 di pga gain setting control bit 1 11 txpd di tx path power down control (active low) 12 amppd 2 di undedicated opamp power down control (active low) 13 rxpd di rx path power down control (active low) 14 pwrvee4 vee power stage ground. 15 pwrvee3 vee power stage ground. 16 paon2 ao tx power amplifier negative output 17 paon1 ao tx power amplifier negative output 18 buffn ao current generator buffer negative output 19 buffp ao current generator buffer positive output 20 paop2 ao tx power amplifier positive output 21 paop1 ao tx power amplifier positive output 22 pwrvee2 vee power stage ground. 23 pwrvee1 vee power stage ground. 24 nc not connected 25 dcfbin ai power amp dc feedback amplifier negative input 26 dcfbip ai power amp dc feedback amplifier positive input 27 qveetx vee quiet ground for tx circuitry 28 txvee3 vee ground for tx path circuitry 29 txvee2 vee ground for tx path circuitry 30 txvee1 vee ground for tx path circuitry 31 txvcc1 vcc +5.0v supply for power amp output stage STLC1512 4/26 32 txvcc2 vcc +5.0v supply for power amp output stage 33 txvcc3 vcc +5.0v supply for tx path circuitry and bias blocks 34 ampout ao undedicated opamp output 35 ampin ai undedicated opamp negative input 36 ampip ai undedicated opamp positive input 37 dcfbon ao power amp dc feedback amplifier negative output 38 dcfbop ao power amp dc feedback amplifier positive output 39 txang ao 2.5v tx buffered reference 40 fpp ao fast path positive output 41 fpn ao fast path negative output 42 paip ai tx power amplifier positive input 43 pain ai tx power amplifier negative input 44 rbias ao reference resistor generating bias current 45 ref2p5 ai externally supplied 2.5v reference 46 nc not connected 47 lpfout ao lpf (low pass filter) op amp output 48 lpfin ai lpf (low pass filter) op amp negative input <1>the values of the components that are connected to the pins are shown in figure 11. <2>if the undedicated opamp is used in the transmit path, amppd can be connected to txpd on the board. if the undedicated opamp is used in the receive path, amppd can be connected to rxpd on the board. this opamp is powered off of txvcc3. table 1. pin description 3.0 functional description the STLC1512 consists of the following functional blocks: n transmit signal path n receive signal path n thermal protection the transmit signal that comes from the afe is fil- tered before it reaches the line driver. STLC1512 contains an opamp that can be utilized as part of this filter. the amppd pin allows this op amp to be pow- ered down independently. the line driver consists of a preamp followed by a current drive power stage. the preamplifier provides large open loop gain while the power stage provides open collector current drive to allow for single supply switching. the center tap of the primary side of the transformer is connected to a supply that can be switched between 5.0v and a low- er supply to realize power savings on a dmt signal. the reference design sets this supply at 3.3v. the line driver can be powered down by a low at the txpd pin. the receive path consists of a programmable gain amplifier (pga) and an active low pass filter. the pga is programmable in four steps. the active low pass filter is composed of an on chip op amp and ex- ternal passive components. the receive signal pass- es through the pga, is low pass filtered and then driven off chip to the afe chip. both the pga and the opamp can be powered down by rxpd signal. a thermal protection circuit has also been implement- ed on the chip to prevent the chip from overheating under fault conditions. 4.0 specifications 4.1 chip specifications the cross-talk specifications are based on the as- sumption that cross-talk should not degrade the sndr of the receive signal. if there is receive cross- talk into the transmit path, this signal will come back through the hybrid balance and cause noise in the re- ceive path. if the signal is undistorted it will cause a small gain and phase error which will not affect per- formance. if it is distorted it will cause an increased 5/26 STLC1512 noise floor which will degrade the sndr of the re- ceive signal. the same is true of the transmit signal. if the signal is undistorted it will show up out of band in the receive path and will not degrade sndr. however, if the transmit signal is distorted by the cross-talk mecha- nism it will show up in the receive band and could re- duce the sndr. the cross-talk numbers are specified from output to output under maximum gain conditions. 4.2 power amplifier performance specifications the power amplifier must be specified with all of the external components in the application diagram. without these components the amplifier will not func- tion correctly. specifications that are measured at the chip are specified as such in the comments. table 3 contains the conditions over which the spec- ifications in table 4 apply. the limits on the specifica- tions in table are valid over all of the ranges specified in table 3. the nominal values of the spec- ification occur at the nominal value of all of the condi- tions in table 3 unless otherwise specified. ... table 2. chip performance specifications description min nom max units comments rx cross-talk into tx undistorted -55 db measured from the active low pass filter output in the receive path to tip and ring. rx cross-talk into tx distorted -73 db measured from the active low pass filter output in the receive path to tip and ring. tx cross-talk into rx undistorted -50 db measured from tip and ring to the active low pass filter output with the maximum gain setting in place. tx cross-talk into rx distorted -86 db measured from tip and ring to the active low pass filter output with the maximum gain setting in place. table 3. power amplifier performance limits description min nom max units comments 1 , 2 gain 19.9 20.1 20.3 db ambient temperature -40 27 85 o c line impedance 80 100 160 w a nominal chip will have no problem driving 200 w or 50 w . supply voltage for txvcc 4.75 5.0 5.25 v <1>nominal specifications are for nominal bias and process <2>maximum and minimum specifications are for worst case process and bias conditions STLC1512 6/26 table 4. power amplifier performance specifications unless otherwise specified nom specs apply to the nom conditions in attribute and the max and min conditions are defined by the process and other spec limits that give these worst case corners. description min nom max goal units comments quiescent current at paop/ pa o n 1 10 15 18 ma the spec is measured as the sum of the currents at poap1+paop2 or paon1+paon2. total quiescent current at output stage 2 20 30 36 ma measured at the center tap of the transformer. input bias current 3 15 m a measured at pin paip/pain. this parameter cannot be measured very accurately. minimum voltage at paop/ paon 4 high current drive 0.85 vpeak measured at pin paop1,2/ pa o n 1 , 2 minimum voltage at paop/ pa o n 5 low current drive 0.70 vpeak measured at pin paop1,2/ pa o n 1 , 2 common mode input voltage range 6 1.6 vcc- 0.5 v measured at pin paip/pain peak output sink current on pin paop and pa o n 7 600 1000 ma this is the sum of the current from paop1 and paop2 or the sum of the currents from paon1 and paon2 power supply rejection see figure 3. slew rate 8 35 v/ m s measured across the 100 ohm line impedance output referred noise voltage 9 78 120 nv/ ? hz measured at f=120khz simulated to be good from 30khz to 540khz. signal to distortion ratio two tone a 10 im2 @ 200 khz im3 @ 100 khz two tone b 7/26 STLC1512 thermal shutdown junction temperature 12 130 150 175 o c only the power amplifier is shut down under overheat condition <1> the quiescent current is the current flowing into pin paop/paon when there is no signal. <2> this is the current drawn from the power supply that is connected to the center tap on the primary side of the transformer. <3> this is the current flowing into the pin pain or paip when there is no signal. the nature of the test set up makes this quan tity very difficult to measure. it is verified through simulation. <4> this will allow the distortion specs to be met while driving a 160w line impedance. this applies for a 550ma output current. the worst case impedance for a nominal chip is 200 w. <5> this spec is meant as an aid in calculating the proper switching point. it applies for a 225ma output current. <6> this is a requirement on the input signal that allows the distortion spec to be met. it is not a testable parameter. the ran ge has been arrived at from simulations. <7> the minimum sink current refers to peak signal current in normal operation. this is tested by placing a 80 w load as the lin e impedance and ensuring that the amplifier still passes the distortion tests. the maximum sink current refers to the current tha t will be delivered if tip and ring are shorted. a nominal chip can drive a 50w load while a worst case chip will drive 80w. <8> slew rate spec is to guarantee that there is no slewing limit on a maximum amplitude sine wave at 540khz. a 100 mv step is placed at the power amp input and the slew rate at the output of the amplifier is measured across the 100 ohm load impedance. <9> measured across the 100 ohm line impedance. this noise spec can be converted to db/hz through the following formula, the effect of the noise in the receive path can be obtained by subtracting the hybrid balance number. <10> two tone distortion is measured with two sine waves with each sine wave at an amplitude of 1/2 full scale (for signal gain of 20.1db, the full scale signal at power amplifier input is 1.05 vp). the two tone distortion requirement is measured from the rm s voltage of a single signal tone to the rms voltage of the distortion product. for the two tone a spec the tones are at f1=500kh z and f2=300khz giving im2=200khz and im3=100khz. for the two tone b the tones are at f1= 500khz and f2=450khz so that im3=550khz. <11> a multi-tone sine wave is used for the ds (down stream) multi-tone test. (the multi-tone signal will be 91 sine waves equal ly spaced from 35x4.3125khz to 125x4.3125khz with a peak-to-rms voltage ratio of 5.3 and an rms voltage equal to 208mv. each tone will have a peak amplitude of 30.8mv) the multi-tone test measures the difference between the power of the test tones and the maximum power of a single distortion product in the given bands. <12> the thermal shut down can not be directly tested in production. it will be investigated at bench and a correlation will be done hermal shutdown temperature. table 4. power amplifier performance specifications n db 10 e n 2 x1000 100 ------------------------- - log = STLC1512 8/26 4.3 programmable gain amplifier (pga) performance specifications it should be noted that the pga and lpf in the receive path must be ac coupled to avoid problems with ampli- fying any offsets. both the pga and the amplifiers are specified in terms of the silicon only. this is to allow the system design to be more flexible. the appendices show how to convert some of the silicon specs to system specs. figure 3. power supply rejection of the power amplifier 1 <1>this is a nominal specification. 6 db of margin should be added to arrive at a worst case spec. table 5. pga performance specifications unless otherwise specified, nom specifications apply for vcc=5.0v, temperature range outlined in table 4.4, nominal process and bias current. max and min performances with 5% variation on vcc, -40 <= t ambient <=85 o c, and worst case process and bias current and a minimum load of 440 w. description min nom max units comments absolute voltage gain 1,2 d=00 d=01 d=10 d=11 11.4 1.4 -5.6 -19.8 11.8 1.8 -5.2 -19.2 12.2 2.2 -4.8 -18.8 db db db db where d is the binary value of the control word [pga1, pga0] gain settings are from the pin pgain to pin pgaout (see application diagram) wdb ( paout ) -40 -60 -80 -100 3.00e+04 1.00e+05 6.00e+05 hz db 9/26 STLC1512 relative gain accuracy 2,3 11.8<--> 1.8db step 1.8<--> -5.2 db step -5.2 <--> -19.2 db step -0.15 -0.17 -0.2 0 0 0 0.15 0.17 0.2 db db db assume a fixed vcc, temperature, and frequency gain variation with temperature STLC1512 10/26 input impedance (over process) 7,8 4.0 5 6.0 k w measure at pin pgain. for all pga gains input impedance (over temperature) 7,9 -10% 10% k w measure at pin pgain. for all pga gains input impedance (over process and temperature) 7,10 3.5 5 6.5 k w measure at pin pgain. for all pga gains input signal level @ pgain 0 v cc +0.1 v single ended input maximum output signal level @ pgaout 11 1.1 vpeak referenced to rxang. for minimum load impedance of 440 ohms. power 12 19 mw active power <1> the absolute gain test should be done at 30khz, 75khz and 120khz with maximum output signal level of 1.1vp. <2> the calculation to show how to determine the gain from the line is given in appendix a. this appendix also shows how to cal culate the gain variations in the application <3> these are chip specs only. the application specs are calculated in appendix a. <4> two tone distortion is measured with two sine waves having an amplitude given in 6. tone one is at f1=500khz and tone two is at f2=300khz, im2 appears at 200khz and im3 appears ar 100khz. <5> a multi-tone sine wave is used for the ds (down stream) multi-tone test. (the multi-tone signal will be 91 sine waves equall y spaced from 35x4.3125khz to 125x4.3125khz with a peak-to-rms ratio of 5.3 and an rms voltage given in table 6. the multi- tone test measures the difference between the rms voltage of a single tone at the output to the rms voltage of the maximum distortion product at the output in the frequency band between 30khz to 120khz. <6> this is the noise referred to the pga input pin pgain. the input noise can be referenced to tip and ring in dbm/hz through t he formula, where ndb is the line noise in dbm/hz, vn is the input referred voltage noise of the pga, h is the hybrid loss (9.54db) and g is the gain from the hybrid output to the input of the pga. see appendix a for calculation of g. appendix b shows plots of the noise performance of the entire receive path as shown in figure 9. <7> these numbers are required to determine the gain variations in the application. <8> the input impedance specified here is the nominal value and the variation is due only to processing. <9> the input impedance specified here is the nominal value and the variation is due only to temperature. this variation is spec ified from the nominal value at 27c. <10> the input impedance specified here is the nominal value with the variation due to both process and temperature. <11> this spec is guaranteed by the distortion test. <12> this power can not be verified independently. it can only be measured as part of the power from the rxvcc supply. table 6. multi-tone sine waves gain setting 2 tone amplitudes multi-tone rms multi-tone amplitudes 00 173 mv 66 mv 9.78 mv 01 550 mv 207 mv 30.7 mv 10 1.125 v 414 mv 61.4 mv 11 1.125 v 414 mv 61.4 mv table 5. pga performance specifications n db 10 100 1000 ------------ - v n 2 ? ?? log g h ++ = 11/26 STLC1512 4.4 amplifier performance specification the two amplifiers on the STLC1512 are identical. one of them is used for the second order active low pass filter that follows the pga in the receive path. the other is an undedicated opamp that can be used either in the transmit or receive paths. the lpf amplifier is powered from the rxvcc supply and is therefore intended to be used in the receive path. it has its positive terminal tied to the receive ac ground (rxang) on chip. the undedicated op amp is powered from txvcc. it is intended for use in the transmit path but could be used in the receive path. using it in the receive path may cause receive noise to be coupled into the transmit path. there should not be an issue with transmit noise coupling into the receive path in either configuration. figure 4. power supply rejection of the pga 1 <1>these curves represent typical performance. 6db of margin is required for worst case. db STLC1512 12/26 table 7. amplifier performance specifications. unless otherwise specified, nom specifications apply for vcc=5v, temperature range outlined in table 3, nominal process and bias current. max and min performances with 5% variation on vcc, -40 <= t junction <=115 o c, and worst case process and bias current parameter min nom max units comments input offset voltage 5 mv unity gain bandwidth 30 50 mhz phase margin 50 degrees gain margin 9 db dc open loop gain 80 db slew rate 25 v / us signal to distortion ratio in negative unity gain 1 two tone a 2 im2 @ 200 khz im3 @ 100 khz two tone b 3 im3 @ 550 khz output ds multi-tone 4 30khz<=f<=120khz 150khz<=f<=550khz <1>the multi tone spec is the spec which defines system performance. the two tone spec is available because it may not be possi ble to create an adequate multi-tone signal with the test hardware. <2>two tone a distortion is measured with two sine waves with each sine wave at an amplitude of 1/2 full scale. tone one is at f1=500khz and tone two is at f2=300khz. <3>two tone b distortion is measured with two sine waves with each sine wave at an amplitude of 1/2 full scale. tone one is at f1=500khz and tone two is at f2=450khz. 89 89 59 89 59 db db db db db maximum output signal level=1.1vp the two tone b spec only applies to the undedicated opamp signal to distortion ratio in positive unity gain. undedicated opamp only. 1,5 two tone a 2 im2 im3 two tone b 3 im3 output ds multi-tone 4 30khz<=f<=120khz 150khz<=f<=550khz 78 78 59 78 59 db db db db db maximum output signal level=1.1vp input referred voltage noise 3.5 5 nv/ ? hz input referred current noise 2pa/ ? hz 13/26 STLC1512 <4>a multi-tone sine wave is used for the ds (down stream) multi-tone test. (the multi-tone signal will be 91 sine waves equall y spaced from 35x4.3125khz to 125x4.3125khz with a peak-to-rms ratio of 5.3, an rms voltage equal to 207mv and a tone amplitude of 30.7mv.) the multi-tone test measures the difference between the rms voltage of a single tone at the output to the rms volta ge of the maximum distortion product at the output in the band of interest. <5>the undedicated op amp specs are available in two configurations since it is undetermined which way the opamp will be used i n the application. the distortion specs for the 2 configurations are very different. figure 5. circuit connection for measuring distortion figure 6. power supply rejection of the amplifier 1 <1>this curve is a nominal simulation. 6 db of margin should be added for worst case. r r negative unity gain positive unity gain + - + - vin vin vdb ( ampoutx ) 10 0 -20 -40 -60 -80 1e+02 1e+08 1e+05 hz db STLC1512 14/26 4.5 supply rating and operating environment 4.5.1 environment conditions 4.5.2 maximum and minimum voltage ratings 4.5.3 power supplies table 8. environment conditions parameter units conditions ambient temperature range (long-term) -40 to +80 o c ambient temperature range (short-term) 1 <1>short-term is defined as no greater than 96 consecutive hours and 15 days per year -40 to +85 c table 9. maximum and minimum voltage ratings pins maximum minimum all vcc pins 6.5v -0.5v all other pins vcc+0.4v -0.4v table 10. power supply v/i (pin names) description min nom max unit comments v(txvcc1..2) supply voltage for power stage 4.75 5.0 5.25 v v(txvcc3) supply voltage for tx path 4.75 5.0 5.25 v v(rxvcc1..2) supply voltage for rx path 4.75 5.0 5.25 v v(pwrvee1..4) ground for pa 0 v v(txvee1..3)) ground for tx path 0 v v(rxvee1..2)) ground for rx path 0 v p(txvcc1..2) current drawn by txvcc1..2 36.6 marms while passing a full scale signal. 1 p(txvcc1..2) current drawn by txvcc1..2 12.8 15.6 marms quiescent current p(txvcc3) current drawn by txvcc3 12 marms while passing a full scale signal. 15/26 STLC1512 4.5.4 power supply noise 4.5.5 references p(rxvcc1..2) current drawn by rxvcc 8.6 marms while passing a full scale signal. 17/26 STLC1512 figure 7. application diagram STLC1512 18/26 appendix a - pga gain calculations the application requires some drop from the output of the hybrid balance to the input of the pga in order to keep the signal level at an acceptable level. (see table 5) the input is reduced by placing a resistor between the output of the hybrid balance network and pgain. this resistor (r ext ) serves two purposes. first, it creates a resistor divider between the hybrid balance and the input. second, it allows a capacitor to be placed across the input of the pga to create a first order low pass filter. this further reduces the signal in long loop cases. the resistor divider is formed by the external resistor and the input impedance of the pga. the gain from the hybrid balance to the output of the pga is therefore given by where g table is the gain number given in table , r input is the input impedance of the pga given in table r ext is the resistance placed between the hybrid balance and pgain. equation can also be used to determine variations over process and temperature. to accomplish this just de- termine the max and min values using the input resistance variation given in table . to convert the noise numbers in table to line referred noise numbers use where n db is the noise on the line in dbm/hz, v n is the input referred noise from table , h is the hybrid loss (9.54db in the reference design), and g is given by 20 r input r input r ext + ---------------------------------- ? ? ?? log g table + n db 10 1000 100 ------------ - v n 2 ? ?? log g h ++ = g20 r input r ext + r input ---------------------------------- ? ? ?? log = 19/26 STLC1512 appendix b - rx path noise performance the following plots show the noise performance of the receive path as it is shown in figure 7. they show the effects of different gain settings as well as typical and worst case performance of the receiver. these noise num- bers are referred to the line. figure 8. noise for various gain settings STLC1512 20/26 appendix c - transmit path noise performance the following plots show the noise performance of the transmit path as it is connected in figure 7. figure 9. transmit filter noise performance at he filter output (nv/ ? hz ) 21/26 STLC1512 figure 10. power amp noise performance at the line (nv/ ? hz) STLC1512 22/26 figure 11. total transmit path noise performance at the line (nv/ ? hz ) 23/26 STLC1512 appendix d - headroom calculation for switching the headroom for switching can be determined from the numbers in table 4. the switching headroom is 0.70 v at low currents (i.e. while on the low supply rail) and 0.85 v at high currents (i.e. while on the high supply rail). the most difficult number to arrive at is the voltage that will appear at the pins paop1,2 and paon1,2. this is a combination of the input voltage, the line impedance and the losses in the transformers. for a 100 w load the maximum signal on the line will be 10.7 v. since we are generating an active 100 w output impedance the voltage on the line for any other load is given by: (eq d.1) where z o is the line impedance and v line is the voltage on the line. there are various losses in the transformers that can be modeled as resistors. to calculate the effect of these losses we must know the current through the load which is given by: (eq d.2) the loss through the line transformer can be modeled as a 2.6 w resistor. there is also a drop across the two 10 w reference resistors. therefore to determine the voltage at the output of the switched transformer we have: (eq d.3) at this point there is some additional current that flows through the hybrid balance network. this current flows through a resistance that is equivalent to 1270 w . therefore the current flowing out of the switched transformer is: (eq d.4) the switched transformer has losses that can be modeled as a 3.6 w resistor and has a 4:1 turns ratio. therefore the voltage at the primary side of the transformer is given by: (eq d.5) where v paox is the voltage at the output pins of the power amp. this is essentially the amount of headroom required to drive a full scale signal into the desired line impedance (z o ). equation d.1 to equation d.5 can be combined to calculate the required headroom to drive a certain impedance. (eq d.6) where v paox is the required headroom to drive v n volts out onto a line with the impedance z o . this equation can be rearranged to calculate the switching threshold. the headroom can be determined from the drop across the diode from the low supply and the low current drive capability of the amplifier given in table (0.70v). (eq d.7) where v supplymin is the minimum value for the lower supply, v headroom is the headroom available on the low supply and v diode is the voltage drop across the diode when it has the appropriate amount of current flowing through it. substituting v headroom in for v paox in equation d.7 you can determine the allowable output voltage v n . this can be scaled to the nominal value of 10.7v (full scale) to determine a switching threshold based on the full scale level of the signal. the headroom calculation is worst at maximum line impedance. there is also a supply rail requirement for the high (5.0v) supply which is based on being able to supply enough current to drive an 80 w line impedance. this is not a trivial calculation and has been based on simulations. the possibility exists that the requirements on the minimum supply voltage may be able to be reduced in the future. v line 2 10.7 () z o 100 z o + ---------------------- - ? ? ?? = i load v line z o ------------ = v swtxout v line 20 2.6 + () i load + = i swtxout i load v swtxout 1270 ---------------------- + = v paox v swtxout 3.6 i swtxout () + 4 --------------------------------------------------------------- = v paox v n 2 ------ z o 20 2.6 3.6 z o 20 2.6 ++ 1270 --------------------------------- - 1 + ? ?? ++ + z o 100 + -------------------------------------------------------------------------------------------------- - ? ? ? ? ?? = v headroom v supplymin 0.70 v diode C C = STLC1512 24/26 appendix e - board issues for heat dissipation the internal temperature of the device must remain below 125 o c. there are a number of ways to ensure that this happens. there are various combinations of maximum ambient temperature and board issues that can contribute to the junction temperature of the devices on the chip. different layout techniques can be used to enhance the thermal coefficient of the package. the following conditions must be true to ensure reliable operation of the line driver. (eq e.1) where t ambient is the maximum ambient temperature that will be experienced by the device, r j is the thermal coefficient as described below and p d is the power dissipation of the chip which is 480mw. the thermal coefficient is determined by the board layout characteristics and the rate that air is being forced across the board. the board layout is defined in 2 ways. one is a 2 layer board with signal layers on the top and bottom. the signal layer has a heat spreading copper plane that spreads from the corner pins of the chip. there are also thermal vias directly under the chip. the second layout is an 8 layer board with signal layers on the top an bottom, 4 copper lattice planes (80% 1 ounce copper) and 2 copper ground planes (solid 1 ounce copper). this layout also has a heat spreading copper plane on the signal layer and thermal vias under the die and in the copper plane. the thermal coefficients for these two different boards are given in table 15. these coefficients are modified based on the amount of air flow over the board.. table 15. thermal coefficients for different board conditions board type r j no air flow ( o c/w) r j 1m/s air flow ( o c/w) r j 3m/s air flow ( o c/w) r j 5m/s air flow ( o c/w) 2 layer 87.2 75.6 63.6 59.4 8 layer 54.7 50.6 48.0 46.1 t ambient r j p d () + 125 o c < 25/26 STLC1512 6.0 mechanical specifications the STLC1512 is packaged in a 48 pin 7x7x1.4mm lowprofile quad flat pack (lqfp) package. body: 7 x 7 x 1.40mm dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.006 0.008 0.010 c 0.09 0.20 0.004 0.008 d 9.00 0.354 d1 7.00 0.276 d3 5.50 0.217 e 0.50 0.020 e 9.00 0.354 e1 7.00 0.276 e3 5.50 0.217 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0 (min.), 3.5?(typ.), 7 (max.) tqfp48 outline and mechanical data information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics a 2000 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sin gapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com 26/26 STLC1512 |
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